NXP Semiconductors /LPC18xx /USB0 /USBMODE_D

Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.

0 (IDLE): Idle

1 (RESERVED): Reserved

2 (DEVICE_CONTROLLER): Device controller

3 (HOST_CONTROLLER): Host controller

Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.

0 (LITTLE_ENDIAN_FIRST): Little endian: first byte referenced in least significant byte of 32-bit word.

1 (BIG_ENDIAN_FIRST_BY): Big endian: first byte referenced in most significant byte of 32-bit word.

Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.

0 (SETUP_LOCKOUTS_ON): Setup Lockouts on

1 (SETUP_LOCKOUTS_OFF): Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)

Stream disable mode The use of this feature substantially limits the overall USB performance that can be achieved.

0 (NOT_DISABLED): Not disabled

1 (DISABLED_SETTING_TH): Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active.

Not used in device mode.

reserved